FIG. 1 provides a high-level abstraction of a portion of a computer server or system, where microprocessor 102 resides on board 104 and communicates with memory 106 on board 108. The communication is by way of striplines on backplane 110. Backplane 110 is connected to boards 104 and 108 by connectors 112. Not shown in FIG. 1 are other memory units and microprocessors, where the various microprocessors and memory units may communicate to one another so as to access or write data and instructions.
Communication of signals over backplane 110 may be modeled by transmission line theory. Often, the signaling is based upon differential signaling, whereby a single bit of information is represented by a differential voltage. For example, FIG. 2a shows drivers 202 and 204 driving transmission lines 206 and 208, respectively. For differential signaling, drivers 202 and 204 drive their respective transmission lines to complementary voltages. Typical curves for the node voltages at nodes n1 and n2 for a bit transition are provided in FIG. 2b, where the bit transition is indicated by a dashed vertical line crossing the time axis. The information content is provided by the difference in the two node voltages.
For short-haul communication, such as for the computer server in FIG. 1, the signal-to-noise ratio is relatively large. If the transmission lines are linear, time-invariant systems having a bandwidth significantly greater than that of the transmitted signal, then a relatively simple receiver architecture may be employed to recover the transmitted data. Such a receiver is abstracted by comparator 210, which provides a logic signal in response to the difference in the two received voltages at ports 212 and 214.
However, every transmission line has a finite bandwidth, and for signal bandwidths that are comparable to or exceed the transmission line (channel) bandwidth, intersymbol interference may present a problem. Furthermore, actual transmission lines may have dispersion, whereby different spectral portions of a signal travel at different speeds. This may result in pulse spreading, again leading to intersymbol interference. As a practical example, for high data rates such as 10 Gbs (Giga bits per second), the transmission lines used with backplanes or motherboards are such that intersymbol interference is present.
Channel equalization is a method in which a filter is employed at a receiver so as to equalize the channel. (A filter may also be employed at a transmitter.) The use of digital filters for channel equalization is well known. A digital filter may operate in a fixed mode, where its corresponding filter response (filter weights) are fixed for a period of time, or it may operate in an adaptation mode, where the filter weights adapt over an adaptation time interval. In practice, a channel equalizer may first be operated in its adaptation mode when a communication session begins, followed by operating in its fixed mode for the remaining of the communication session, or perhaps alternating between fixed mode and adaptation mode during a communication session.
Portions of a filter architecture may be used for both fixed mode and adaptation mode operation. FIG. 3 shows a known high-level filter architecture. Functional blocks 302 and 304 represent V-I converters and current multipliers, respectively. A received voltage is sampled at various times to provide input voltages to V-I converters 302, where each V-I converter receives a sample at different times. (For simplicity, sampling capacitors are not shown.) A filter tap is implemented by a V-I converter followed by a current multiplier. The current multiplication implemented by a current multiplier provides a weighting function, with different current multipliers having in general different multipliers. The number of V-I converter, current multiplier pairs is the number of filter taps implemented. The outputs of current multipliers 304 are provided to a current summing junction 306, followed by latch 308. Latch 308 provides a comparison function, so that the output of latch 308 is binary.
In practice, the filter structure of FIG. 3 may be used in a differential signaling scheme, as discussed with respect to FIGS. 2a and 2b. In such a case, it should be noted that the inputs and outputs of the various analog functional blocks in FIG. 3 are differential signals. For example, the input to latch 308 may be a differential signal, say V1 and V2, where ideally the output of latch 308 is HIGH or LOW depending upon the algebraic sign of (V1−V2). In practice, latch 308 will have an input current offset, so that an offset current provided by current source 310 and current multiplier 312 is provided to mitigate the offset of latch 308.
The combination of V-I converters 302 and current multipliers 304 constitutes a weighted tap delay line, and together with current summing junction 306, provides a FIR (Finite Impulse Response) filter. (Latch 308, together with current source 310 and current multiplier 312 to provide an offset, provides a detection function, where the output of latch 308 is a Boolean 1 or 0.) V-I converters 302 and current multipliers 304 may also form part of an adaptive filter structure, where the various current multipliers are controlled digitally by adapter functional block 314.
To implement an adaptive filter, a training sequence functional unit 315 stores at the receiver a training sequence. During adaptation, this known training sequence is transmitted by the transmitter. On the receive side during adaptation, the training sequence is used to modulate the output of current multiplier 316 and current source 318, indicated by functional multiplier unit 320, which is then provided to current summing junction 306 to provide an error signal. Multiplier 316 is utilized to properly scale the current provided to summing junction 306, in which case the training sequence may be taken as a sequence having values 1 or −1.
The resulting error signal is utilized by adapter 314 to adjust the various current multipliers, so as to effect any number of adaptive filtering algorithms, such as for example a LMS (least means square) type of adaptive algorithm. Some adaptive algorithms also require adapter 314 to directly utilize the training sequence, as indicated in FIG. 3 by a direct connection from training sequence functional unit 315 to adapter 314. In practice, the analog portion of the circuit architecture in FIG. 3 may be operated at a much higher data rate than that of the digital logic portion, in which case it is desirable to have two clock domains, where dashed line 320 indicates a clock domain boundary separating the high-speed analog circuit portion from the low-speed digital circuit portion.
With the filter architecture of FIG. 3, setting current multiplier 320 should be performed within the analog clock domain, yet the training sequence available for setting current multiplier 320 is within the slower, digital clock domain. Consequently, the filter architecture of FIG. 3 may result in violation of clock domain boundary 320.